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dc.contributor.otherPreservation Department, Stony Brook University Libraries.en_US
dc.contributor.otherCataloging & Metadata Department, Stony Brook University Libraries.en_US
dc.identifier.urihttp://hdl.handle.net/1951/37286
dc.identifier.urihttp://hdl.handle.net/11401/65127
dc.formatMonograph.en_US
dc.format.extent7317118 bytes
dc.format.mediumElectronic Resource.en_US
dc.language.isoen_US
dc.rightsAll Rights Reserved. Stony Brook University.en_US
dc.typeTechnical Reporten_US
dcterms.creatorCarlson, Bradley S.en_US
dcterms.creatorChen, C.Y. Roger
dcterms.dateAccepted2007-07-17T16:40:33Z
dcterms.dateAccepted2015-04-24T14:26:00Z
dcterms.dateSubmitted2007-07-17T16:40:33Z
dcterms.dateSubmitted2015-04-24T14:26:00Z
dcterms.extentleave(s) : ill; 28 cm.en_US
dcterms.formatapplication/pdf
dcterms.issued1992en_US
dcterms.provenanceMade available in DSpace on 2007-07-17T16:40:33Z (GMT). No. of bitstreams: 1 CEAS--617.pdf: 7317118 bytes, checksum: 39e90e765cc692d3a0bea2a094f2ed37 (MD5) Previous issue date: 1992en
dcterms.provenanceMade available in DSpace on 2015-04-24T14:26:00Z (GMT). No. of bitstreams: 3 CEAS--617.pdf.jpg: 1759 bytes, checksum: 22d87cec3d21bed56e87eb6ef5ddf1d5 (MD5) CEAS--617.pdf.txt: 39349 bytes, checksum: f2b74c8fd49544801d61944df0e90f94 (MD5) CEAS--617.pdf: 7317118 bytes, checksum: 39e90e765cc692d3a0bea2a094f2ed37 (MD5) Previous issue date: 1992en
dcterms.publisherStony Brook, NY.en_US
dcterms.publisherStony Brook, N.Y.: State University of New York at Stony Brook, College of Engineering.en_US
dcterms.publisherStony Brook University.en_US
dcterms.titleA transistor reordering algorithm for the performance optimization of CMOS digital circuitsen_US
dc.description.contributorThe content contained herein is maintained and curated by the Preservation Department.en_US
dc.description.contributorThis record is revised and maintained by the content administrators from the Cataloging & Metadata Department.en_US


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