| dc.identifier.uri | http://hdl.handle.net/11401/71075 | |
| dc.identifier.uri | http://hdl.handle.net/1951/57605 | |
| dc.description.sponsorship | This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree. | en_US |
| dc.format | Monograph | |
| dc.format.medium | Electronic Resource | en_US |
| dc.language.iso | en_US | |
| dc.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dc.type | Thesis | |
| dcterms.abstract | Three primary techniques for manufacturing through silicon vias (TSVs), viafirst,
via-middle, and via-last, have been analyzed and compared to distribute power
in a three-dimensional (3-D) processor-memory system with nine planes. Due to
distinct fabrication techniques, these TSV technologies require significantly different
design constraints, as investigated in this work. A valid design space that
satisfies the peak power supply noise while minimizing area overhead is identified
for each technology. It is demonstrated that the area overhead of a power distribution
network with via-first TSVs is approximately 9% as compared to less than
2% in via-middle and via-last technologies. Despite this drawback, a via-first based
power network is typically overdamped and the issue of resonance is alleviated. A
via-last based power network, however, exhibits a relatively low damping factor and
the peak noise is highly sensitive to number of TSVs and decoupling capacitance. | |
| dcterms.available | 2012-10-10T16:17:28Z | |
| dcterms.available | 2015-04-24T14:45:51Z | |
| dcterms.contributor | Salman, Emre | en_US |
| dcterms.creator | Satheesh, Suhas M. | |
| dcterms.dateAccepted | 2012-10-10T16:17:28Z | |
| dcterms.dateAccepted | 2015-04-24T14:45:51Z | |
| dcterms.dateSubmitted | 2012-10-10T16:17:28Z | |
| dcterms.dateSubmitted | 2015-04-24T14:45:51Z | |
| dcterms.description | Department of Electrical Engineering. | en_US |
| dcterms.format | Monograph | |
| dcterms.format | Application/PDF | en_US |
| dcterms.identifier | http://hdl.handle.net/11401/71075 | |
| dcterms.identifier | http://hdl.handle.net/1951/57605 | |
| dcterms.issued | 2012-05-01 | |
| dcterms.language | en_US | |
| dcterms.provenance | Submitted by Karen D'Angelo (kdangelo@notes.cc.sunysb.edu) on 2012-10-10T16:17:28Z
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Satheesh_grad.sunysb_0771M_10918.pdf: 1699631 bytes, checksum: 450f6f19e09838dcb55e1e678c7ad54c (MD5)
Previous issue date: 2012-05-01 | en |
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Previous issue date: 2012-05-01 | en |
| dcterms.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dcterms.subject | 3-D IC, Decoupling capacitor, Peak noise, Power delivery, Processor-memory, TSV | |
| dcterms.title | Power Distribution in 3-D Processor-Memory Stacks | |
| dcterms.type | Thesis | |
