| dc.identifier.uri | http://hdl.handle.net/1951/59853 | |
| dc.identifier.uri | http://hdl.handle.net/11401/71403 | |
| dc.description.sponsorship | This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree. | en_US |
| dc.format | Monograph | |
| dc.format.medium | Electronic Resource | en_US |
| dc.language.iso | en_US | |
| dc.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dc.type | Thesis | |
| dcterms.abstract | Three primary techniques for manufacturing through silicon vias (TSVs), via-first, via-middle, and via-last, have been analyzed and compared to distribute power in a three-dimensional (3-D) processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this work. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to number of TSVs and decoupling capacitance. | |
| dcterms.available | 2013-05-22T17:35:33Z | |
| dcterms.available | 2015-04-24T14:47:25Z | |
| dcterms.contributor | Salman, Emre | en_US |
| dcterms.contributor | Stanacevic, Milutin. | en_US |
| dcterms.creator | Satheesh, Suhas Mysore | |
| dcterms.dateAccepted | 2013-05-22T17:35:33Z | |
| dcterms.dateAccepted | 2015-04-24T14:47:25Z | |
| dcterms.dateSubmitted | 2013-05-22T17:35:33Z | |
| dcterms.dateSubmitted | 2015-04-24T14:47:25Z | |
| dcterms.description | Department of Electrical Engineering | en_US |
| dcterms.extent | 55 pg. | en_US |
| dcterms.format | Application/PDF | en_US |
| dcterms.format | Monograph | |
| dcterms.identifier | Satheesh_grad.sunysb_0771M_10918 | en_US |
| dcterms.identifier | http://hdl.handle.net/1951/59853 | |
| dcterms.identifier | http://hdl.handle.net/11401/71403 | |
| dcterms.issued | 2012-05-01 | |
| dcterms.language | en_US | |
| dcterms.provenance | Made available in DSpace on 2013-05-22T17:35:33Z (GMT). No. of bitstreams: 1
Satheesh_grad.sunysb_0771M_10918.pdf: 1454765 bytes, checksum: 11d7fcbe4994eaccc640f954d01525ff (MD5)
Previous issue date: 1 | en |
| dcterms.provenance | Made available in DSpace on 2015-04-24T14:47:25Z (GMT). No. of bitstreams: 3
Satheesh_grad.sunysb_0771M_10918.pdf.jpg: 1894 bytes, checksum: a6009c46e6ec8251b348085684cba80d (MD5)
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Satheesh_grad.sunysb_0771M_10918.pdf: 1454765 bytes, checksum: 11d7fcbe4994eaccc640f954d01525ff (MD5)
Previous issue date: 1 | en |
| dcterms.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dcterms.subject | Electrical engineering | |
| dcterms.subject | 3-D IC, Decoupling capacitor, Peak noise, Power delivery, Processor-memory, TSV | |
| dcterms.title | POWER DISTRIBUTION IN TSV BASED 3-D PROCESSOR-MEMORY STACKS | |
| dcterms.type | Thesis | |
