| dc.identifier.uri | http://hdl.handle.net/1951/60232 | |
| dc.identifier.uri | http://hdl.handle.net/11401/71499 | |
| dc.description.sponsorship | This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree. | en_US |
| dc.format | Monograph | |
| dc.format.medium | Electronic Resource | en_US |
| dc.language.iso | en_US | |
| dc.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dc.type | Dissertation | |
| dcterms.abstract | The objective of this dissertation is to design and evaluate ultra-fast energy-efficient 32-bit integer and single-precision floating-point multipliers implemented with Rapid Single Flux Quantum (RSFQ) superconductor technology. Our goals in both multiplier designs were to design a wide datapath multipliers operating in 10 GHz+ frequencies with lowest possible latency and complexity below 100k Josephson junctions when implemented with Hypres 1.5 um 4.5 kA/cm2 fabrication process. To achieve this goal, various design techniques such as synchronous pipelining, asynchronous co-flow, and wave-pipelining are analyzed and applied throughout the design process. First, we have a brief look at CMOS computing with its power and clock frequency challenges. Then, superconductor technology is introduced, followed by a description of RSFQ logic. Next, traditional design and sequencing techniques for multiplier will be discussed. After a brief review of existing superconductor multipliers, the cell-level design of our 32-bit integer and floating-point multipliers will be presented. The microarchitectures and implementations of the 32-bit multipliers are discussed in detail along with the choice of sequencing techniques used. Our multipliers were designed and evaluated using a SBU VHDL RSFQ cell-library tuned to the Hypres 1.5 um 4.5kA/cm2 fabrication process. The simulation results for the 32-bit integer and floating-point multipliers will be presented along with statistical data about each design. Finally, we will present the design and experimental test results of an 8-bit integer RSFQ multiplier implemented with the Japanese CONNECT cell library and fabricated with ISTEC 1.0 um 10 kA/cm2 technology. | |
| dcterms.available | 2013-05-24T16:38:16Z | |
| dcterms.available | 2015-04-24T14:47:45Z | |
| dcterms.contributor | Doboli, Alexander | en_US |
| dcterms.contributor | Dorojevets, Mikhail | en_US |
| dcterms.contributor | Hong, Sangjin Wong, Jennifer L. | en_US |
| dcterms.creator | Kasperek, Artur Krzysztof | |
| dcterms.dateAccepted | 2013-05-24T16:38:16Z | |
| dcterms.dateAccepted | 2015-04-24T14:47:45Z | |
| dcterms.dateSubmitted | 2013-05-24T16:38:16Z | |
| dcterms.dateSubmitted | 2015-04-24T14:47:45Z | |
| dcterms.description | Department of Computer Engineering | en_US |
| dcterms.extent | 116 pg. | en_US |
| dcterms.format | Monograph | |
| dcterms.format | Application/PDF | en_US |
| dcterms.identifier | http://hdl.handle.net/1951/60232 | |
| dcterms.identifier | http://hdl.handle.net/11401/71499 | |
| dcterms.issued | 2012-05-01 | |
| dcterms.language | en_US | |
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Previous issue date: 1 | en |
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StonyBrookUniversityETDPageEmbargo_20130517082608_116839.pdf: 41286 bytes, checksum: 425a156df10bbe213bfdf4d175026e82 (MD5)
Previous issue date: 1 | en |
| dcterms.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dcterms.subject | Computer engineering à Computer science à Electrical engineering | |
| dcterms.subject | multipliers, RSFQ, superconductors | |
| dcterms.subject | Computer engineering Ð Computer science Ð Electrical engineering | |
| dcterms.title | 32-bit Superconductor Integer and Floating-Point Multipliers | |
| dcterms.type | Dissertation | |
