| dc.identifier.uri | http://hdl.handle.net/1951/56102 | |
| dc.identifier.uri | http://hdl.handle.net/11401/71679 | |
| dc.description.sponsorship | This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree. | en_US |
| dc.format | Monograph | |
| dc.format.medium | Electronic Resource | en_US |
| dc.language.iso | en_US | |
| dc.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dc.type | Dissertation | |
| dcterms.abstract | Prior to early this century, the semiconductor microprocessor can be scaled according to the Moore's law, basically doubling its performance in every 18 months. Only recently, the energy efficiency of semiconductor integrated circuits has become a concern than their computational capabilities since their power dissipation scales nonlinear with clock frequency. The specific energy dissipation per logic operation for a modern semiconductor computer is still over 6 orders of magnitude above the thermodynamic threshold k<sub>B</sub>Tln2. It has been known for a long time that this thermodynamic limit on the energy dissipation per logic operation can be overcome by physically and logically reversible circuits. Reversible circuits based on nSQUIDs (negative SQUIDs) or dc SQUIDs (superconducting quantum interference device) with negative mutual inductance between the arms of the SQUID loop, are introduced and investigated in this thesis. First test reversible circuit contains one 8-stage shift register, cells that transfer the input data to the outputs. Dynamic of this circuit illustrates unique properties which agree well with theoretical analysis. Based on the knowledge from the study of shift register, a new timing belt clocking scheme built upon the moving vortices along long Josephson junction (LJJ) is introduced and analyzed. The test circuits for this new scheme contain two 8-stage shift registers, one with direct and the other with inverted outputs. The energy dissipation per nSQUID gate per bit measured for these test circuits at 4 K temperature is already below the thermodynamic threshold. A family of logical gates based on the new timing belt and nSQUIDs shift register are continued to be developed and these gates are capable of fundamentally low energy dissipation and the ability to operate in both irreversible and reversible modes. Moreover, the extremely low energy dissipation in these circuits makes them a natural candidate to support circuitry working in quantum mode with unique advantages. | |
| dcterms.available | 2012-05-17T12:22:02Z | |
| dcterms.available | 2015-04-24T14:48:30Z | |
| dcterms.contributor | Vasili K. Semenov. | en_US |
| dcterms.contributor | Dmitri Averin | en_US |
| dcterms.contributor | Gene Sprouse | en_US |
| dcterms.contributor | Peter Shkolnikov. | en_US |
| dcterms.creator | Ren, Jie | |
| dcterms.dateAccepted | 2012-05-17T12:22:02Z | |
| dcterms.dateAccepted | 2015-04-24T14:48:30Z | |
| dcterms.dateSubmitted | 2012-05-17T12:22:02Z | |
| dcterms.dateSubmitted | 2015-04-24T14:48:30Z | |
| dcterms.description | Department of Physics | en_US |
| dcterms.format | Application/PDF | en_US |
| dcterms.format | Monograph | |
| dcterms.identifier | http://hdl.handle.net/1951/56102 | |
| dcterms.identifier | Ren_grad.sunysb_0771E_10445.pdf | en_US |
| dcterms.identifier | http://hdl.handle.net/11401/71679 | |
| dcterms.issued | 2011-05-01 | |
| dcterms.language | en_US | |
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Previous issue date: 1 | en |
| dcterms.provenance | Made available in DSpace on 2015-04-24T14:48:30Z (GMT). No. of bitstreams: 3
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Previous issue date: 1 | en |
| dcterms.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dcterms.subject | Physics | |
| dcterms.subject | Reversible computing, Superconducting | |
| dcterms.title | Physically and Logically Reversible Superconducting Circuit | |
| dcterms.type | Dissertation | |
