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dc.identifier.other839
dc.identifier.urihttp://hdl.handle.net/11401/75982
dc.language.isoen_USen_US
dc.typeTechnical Reporten_US
dcterms.creatorCho, Shenghsun
dcterms.creatorPatel, Mrunal
dcterms.creatorKaladagi, Basavaraj
dcterms.creatorChen, Han
dcterms.creatorPalit, Tapti
dcterms.creatorFerdman, Michael
dcterms.creatorMilder, Peter
dcterms.dateAccepted2017-08-22T13:54:33Z
dcterms.dateSubmitted2017-08-22T13:54:33Z
dcterms.description;CEAS Technical Report; 839
dcterms.issued2017en_US
dcterms.provenanceSubmitted by Jason Torre (fjason.torre@stonybrook.edu) on 2017-08-22T13:54:32Z No. of bitstreams: 1 Tech_Report_CEAS_839.pdf: 217238 bytes, checksum: 97c52354bb577c9479e1431893cdcc56 (MD5)en
dcterms.provenanceMade available in DSpace on 2017-08-22T13:54:33Z (GMT). No. of bitstreams: 1 Tech_Report_CEAS_839.pdf: 217238 bytes, checksum: 97c52354bb577c9479e1431893cdcc56 (MD5) Previous issue date: 2017-08-16en
dcterms.publisherDepartment of Computer Scienceen_US
dcterms.titleA VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAsen_US


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