| dc.identifier.other | 839 | |
| dc.identifier.uri | http://hdl.handle.net/11401/75982 | |
| dc.language.iso | en_US | en_US |
| dc.type | Technical Report | en_US |
| dcterms.creator | Cho, Shenghsun | |
| dcterms.creator | Patel, Mrunal | |
| dcterms.creator | Kaladagi, Basavaraj | |
| dcterms.creator | Chen, Han | |
| dcterms.creator | Palit, Tapti | |
| dcterms.creator | Ferdman, Michael | |
| dcterms.creator | Milder, Peter | |
| dcterms.dateAccepted | 2017-08-22T13:54:33Z | |
| dcterms.dateSubmitted | 2017-08-22T13:54:33Z | |
| dcterms.description | ;CEAS Technical Report; 839 | |
| dcterms.issued | 2017 | en_US |
| dcterms.provenance | Submitted by Jason Torre (fjason.torre@stonybrook.edu) on 2017-08-22T13:54:32Z
No. of bitstreams: 1
Tech_Report_CEAS_839.pdf: 217238 bytes, checksum: 97c52354bb577c9479e1431893cdcc56 (MD5) | en |
| dcterms.provenance | Made available in DSpace on 2017-08-22T13:54:33Z (GMT). No. of bitstreams: 1
Tech_Report_CEAS_839.pdf: 217238 bytes, checksum: 97c52354bb577c9479e1431893cdcc56 (MD5)
Previous issue date: 2017-08-16 | en |
| dcterms.publisher | Department of Computer Science | en_US |
| dcterms.title | A VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAs | en_US |
