| dc.identifier.uri | http://hdl.handle.net/11401/77484 | |
| dc.description.sponsorship | This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree. | en_US |
| dc.format | Monograph | |
| dc.format.medium | Electronic Resource | en_US |
| dc.language.iso | en_US | |
| dc.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dc.type | Thesis | |
| dcterms.abstract | With higher integration, power has become a primary concern for IC design. Clock signal has the highest switching activity and can be responsible for up to 40\% of the overall power dissipation due to large clock network capacitance. This dissertation presents an approach to reduce this power consumption by providing a 30\% reduction in the clock swing, which is accomplished by custom reduced-swing buffers. The objective is to reduce the clock swing without implementing an additional low supply voltage, while also satisfying the slew constraints at multiple process, voltage and temperature (PVT) corners. The low swing buffer is designed using 1V 45nm NCSU technology and the clock frequency considered for this analysis is 1.5GHz. As compared to a conventional buffer, approximately 14\% reduction in the dynamic power consumption is achieved while driving a load capacitance of 50fF and maintaining the same clock slew. A novel D flip-flop (DFF) architecture that can operate with a low swing clock is also proposed and compared with existing designs. These architectures are simulated considering a clock and data frequency of 1.5GHz and 150MHz, respectively. In comparison with the other low swing topologies, the proposed low swing DFF topology provides an average reduction of 33.6\% and 39.5\% in, respectively, the overall dynamic power dissipation and power-delay product. The robustness of the DFF architectures is also evaluated for different PVT corners. This comparative analysis demonstrates an average improvement of 19.34\% and 38.91\% in, respectively, CLK-to-Q delay and dynamic power dissipation for the proposed topology. Finally, a low swing clock distribution network is designed and analyzed by combining the custom reduced swing buffers and the proposed DFF architecture. Reliable operation is demonstrated considering a large fan-out of 50 DFFs at the output of the reduced swing buffers. | |
| dcterms.available | 2017-09-20T16:52:47Z | |
| dcterms.contributor | Salman, Emre | en_US |
| dcterms.contributor | Stanacevic, Milutin. | en_US |
| dcterms.creator | Rathore, Mallika | |
| dcterms.dateAccepted | 2017-09-20T16:52:47Z | |
| dcterms.dateSubmitted | 2017-09-20T16:52:47Z | |
| dcterms.description | Department of Electrical Engineering. | en_US |
| dcterms.extent | 46 pg. | en_US |
| dcterms.format | Monograph | |
| dcterms.format | Application/PDF | en_US |
| dcterms.identifier | http://hdl.handle.net/11401/77484 | |
| dcterms.issued | 2015-08-01 | |
| dcterms.language | en_US | |
| dcterms.provenance | Made available in DSpace on 2017-09-20T16:52:47Z (GMT). No. of bitstreams: 1
Rathore_grad.sunysb_0771M_11914.pdf: 2226426 bytes, checksum: 488a694ed03dd91d77513cdd866fd80e (MD5)
Previous issue date: 2014 | en |
| dcterms.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dcterms.subject | Engineering | |
| dcterms.title | Design and Analysis of Custom Clock Buffers and a D Flip-Flop for Low Swing Clock Distribution Networks | |
| dcterms.type | Thesis | |
