| dc.identifier.uri | http://hdl.handle.net/11401/77486 | |
| dc.description.sponsorship | This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree. | en_US |
| dc.format | Monograph | |
| dc.format.medium | Electronic Resource | en_US |
| dc.language.iso | en_US | |
| dc.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dc.type | Thesis | |
| dcterms.abstract | Modern reconfigurable logic devices are often multi-core and multi-processor architectures with complex intra-processor logic. To fully utilize the raw power of these devices is an arduous task; mapping design data-flows to such devices in a way that will maximize their performance involves careful consideration of a number of parameters, and is the subject of a good amount of research. This thesis presents a novel design, which uses the technique of buffer-based dataflow, a representation technique for realizing data-centric applications in reconfigurable platforms, to map complex logic systems with multiple processing elements to a reconfigurable target architecture having multi-core processors or multiple processors. The use of multi-core processors requires careful synchronization between the processing elements and we propose employing the buffer-based dataflow technique in conjunction with a controller to map the processing logic onto the reconfigurable platform and deal with the synchronization issues. The logic is implemented using a series of buffers and interconnections, and these are controlled by a top-level global controller, responsible for their configuration and reconfiguration as well as path selection to enable dynamic switching between designs. The dynamic reconfigurability gained from our approach allows us to map multiple processing elements onto a single core and switch between them during run-time while maximizing performance. The proposed design is evaluated with SystemC and Xilinx ISE. | |
| dcterms.available | 2017-09-20T16:52:48Z | |
| dcterms.contributor | Hong, Sangjin | en_US |
| dcterms.contributor | Doboli, Alex. | en_US |
| dcterms.creator | Tiwari, Sumit Suresh | |
| dcterms.dateAccepted | 2017-09-20T16:52:48Z | |
| dcterms.dateSubmitted | 2017-09-20T16:52:48Z | |
| dcterms.description | Department of Electrical Engineering. | en_US |
| dcterms.extent | 67 pg. | en_US |
| dcterms.format | Monograph | |
| dcterms.format | Application/PDF | en_US |
| dcterms.identifier | http://hdl.handle.net/11401/77486 | |
| dcterms.issued | 2014-12-01 | |
| dcterms.language | en_US | |
| dcterms.provenance | Made available in DSpace on 2017-09-20T16:52:48Z (GMT). No. of bitstreams: 1
Tiwari_grad.sunysb_0771M_12181.pdf: 3136869 bytes, checksum: bc24e1410c0537417a811655714b1ef5 (MD5)
Previous issue date: 1 | en |
| dcterms.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dcterms.subject | BBDF, FPGA, Reconfigurable, SystemC | |
| dcterms.subject | Engineering | |
| dcterms.title | Reconfigurable Architecture for Mixed Processing Elements with Buffer Based Representation | |
| dcterms.type | Thesis | |
