| dc.identifier.uri | http://hdl.handle.net/11401/77827 | |
| dc.description.sponsorship | This work is sponsored by the Stony Brook University Graduate School in compliance with the requirements for completion of degree. | en_US |
| dc.format | Monograph | |
| dc.format.medium | Electronic Resource | en_US |
| dc.language.iso | en_US | |
| dc.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dc.type | Dissertation | |
| dcterms.abstract | Cloud-scale data centers increasingly use a rack rather than a machine as the basic building block to provide vital support for applications. To meet the diverse range of service requirements, the concept of disaggregated rack architecture has been proposed recently, in which a rack consists not of a set of self-contained hosts, but of a CPU/memory pool, a disk pool, and a network interface (NIC) pool, which are connected through a high-bandwidth and low-latency rack-area network. A major deployment advantage of the disaggregated rack architecture is that it allows different system components, i.e. CPU, memory, disk, and NIC, to be upgraded according to their own technology cycle. By consolidating each type of system components, it also enables more efficient and flexible resource allocation and utilization. This dissertation proposes Marlin, a memory-based rack area network architecture that takes a PCIe-based network, originally designed for intra-host backplane in a single machine and extends it into a inter-host backplane for communication in a data center rack. By virtue of being based on PCIe, Marlin presents a memory-based addressing model for both I/O device sharing among multiple hosts and inter-host communications, and as a result offers hardware-based remote direct memory access (HRDMA) as a first-class communications primitive between servers within a rack. Marlin supports socket-based communications for legacy network applications and cross-machine zero memory copying for applications designed specifically to take full advantage of Marlin. Finally, Marlin is positioned as an NFV (Network Function Virtualization) platform and proposes a fully direct interrupt delivery hypervisor which minimizes the performance overhead associated with I/O virtualization, a key consideration in NFV. Empirical measurements on a fully operational Marlin prototype based on 4-lane Gen3 PCIe technology show that the one-way kernel-to-kernel latency is 8.5μ sec and the end-to-end sustainable TCP throughput is 19.6 Gbps. | |
| dcterms.available | 2017-09-26T17:08:56Z | |
| dcterms.contributor | Das, Samir R. | en_US |
| dcterms.contributor | Chiueh, Tzi-cker | en_US |
| dcterms.contributor | Ferdman, Michael | en_US |
| dcterms.contributor | Teng, Tian-Lih. | en_US |
| dcterms.creator | Tu, Cheng-Chun | |
| dcterms.dateAccepted | 2017-09-26T17:08:56Z | |
| dcterms.dateSubmitted | 2017-09-26T17:08:56Z | |
| dcterms.description | Department of Computer Science. | en_US |
| dcterms.extent | 113 pg. | en_US |
| dcterms.format | Application/PDF | en_US |
| dcterms.format | Monograph | |
| dcterms.identifier | http://hdl.handle.net/11401/77827 | |
| dcterms.identifier | Tu_grad.sunysb_0771E_11764.pdf | en_US |
| dcterms.issued | 2014-05-01 | |
| dcterms.language | en_US | |
| dcterms.provenance | Submitted by Jason Torre (fjason.torre@stonybrook.edu) on 2017-09-26T17:08:56Z
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Tu_grad.sunysb_0771E_11764.pdf: 2966481 bytes, checksum: d9a5aecbc664fb36483eacba306a59b6 (MD5) | en |
| dcterms.provenance | Made available in DSpace on 2017-09-26T17:08:56Z (GMT). No. of bitstreams: 1
Tu_grad.sunysb_0771E_11764.pdf: 2966481 bytes, checksum: d9a5aecbc664fb36483eacba306a59b6 (MD5)
Previous issue date: 2014-05-01 | en |
| dcterms.publisher | The Graduate School, Stony Brook University: Stony Brook, NY. | |
| dcterms.subject | Computer science | |
| dcterms.subject | I/O Virtualization, MR-IOV, Network Function Virtualization, Non-Transparent Bridge, PCI Express, Rack Disaggregation | |
| dcterms.title | Memory-Based Rack Area Networking | |
| dcterms.type | Dissertation | |
